This invention relates to semiconductor manufacturing generally and more specifically to thermal processing of substrates used to make semiconductor devices.
In the fabrication of different types of advanced semiconductor devices very rapid thermal processing is becoming a critical need. Device applications include diffusion and annealing of implanted semiconductors to form high conductivity structures in substrates; annealing of a number of different materials used in CMOS logic devices and DRAM memory devices as well as processing specialty compound semiconductor devices. A general requirement for many such advanced devices is to very rapidly raise the temperature of the surface and then very rapidly cool-down the surface to enable a diffusion or anneal process without degrading other characteristics of the device materials.
Application of Shallow Junction and Channel Formation in Silicon Devices
There exists a manufacturing need to form very shallow, very high conductivity structures in silicon logic and memory devices with critical pattern dimensions of 0.13 microns and below. Critical shallow high conductivity structures are used in logic devices, source and drain connection junctions and in gate channels; and in silicon junctions for memory devices. Need for a production means to make shallow, highly conductive paths in the range of 40-20 nm depth are projected by 2003. Means to produce junction and channel depths of less than 10 nm are being investigated by many.
Thermal Budget Limitation on Shallow Junction and Channel Formation
To form high conductivity shallow paths in single crystal silicon, a thermal processing step is required. The two methods of driving the doping material into the single crystal silicon so that the doped crystal becomes highly conductive are: (1) implantation of the doping material into the silicon by accelerating the doping atoms into the silicon surface with sufficient energy, followed by a high temperature anneal to repair the crystal damage by the implant process; and (2) diffusion of the doping atoms into the silicon by having a high concentration of doping material on the silicon surface and raising the silicon temperature so that the doping material-diffuses into the silicon. The seed doping material may be in a layer deposited on the silicon surface or may be in the gas at the surface of the wafer.
If shallow high conductivity paths are to be formed there is a maximum allowable xe2x80x9cthermal budgetxe2x80x9d for a given depth of the doping material responsible for the conductivity. Two factors that relate to obtaining very high conductivity shallow structures are: diffusion rates and concentration of the doping atoms in the silicon.
The diffusion rate of a doping material into silicon follows an exponential type dependence on temperature. For a high temperature requirement (e.g., 1200xc2x0 C.), the doping atoms will rapidly diffuse into the silicon and in a short time a shallow highly conductive area can be obtained.
On the other hand, at a relatively low temperature for diffusion into silicon, (e.g., 900xc2x0 C.), a long diffusion time is required that gives a concentration doping gradient that extends relatively deep into the silicon. At the same time other doped areas in the device will diffuse out from their respective initial doping areas.
Consequently, very shallow doping requires a short time duration high temperature pulse. Ideally, the pulse would be a spike that rapidly rises to, and falls from, a high temperature. Similarly, for annealing, crystal damage resulting from a shallow implantation of doping material, a short high temperature pulse is required to maintain a sharply defined, shallow conductive area having a steep concentration gradient at the conductive area boundary. To obtain a short high temperature pulse in the wafer, a means is needed for a well controlled, very rapid, high heat input to the wafer.
High electrical conductivity structures in silicon semiconductor devices are in a non-equilibrium concentration regime. The concentration of doping atoms in the silicon structure is greater than the solubility of the doping material at ambient, operating temperature. Diffusing-or annealing the doping atoms at a high temperature and then cooling the silicon rapidly enough to xe2x80x9cfreezexe2x80x9d the impurity doping atoms into a single crystal structure, achieves this. In this way the doping concentration is set by the solubility of the doping atoms in silicon at the peak process temperature. A higher concentration of doping atoms in a single crystal structure gives a higher electrical conductivity.
Current Methods Under Investigation for Shallow Junction and Channel Formation
Ion implantation and anneal:
A high current, low energy ion implanter implants doping atoms to the required depth and concentration followed by a rapid thermal anneal of the damage. Two rapid anneal methods now used are radiant Rapid Thermal Processing (RTP) and fast furnace anneal RTP. Radiant RTP systems are reported to obtain a temperature rise rate of up to 300xc2x0 C./sec, but significantly slower cool time, see the following paragraph and also FIG. 6. Issues with this approach for future device generations requiring shallow implants and diffusion are:
Ion implanters have high capital cost
Limitations to current production Radiant RTP, see following paragraph
Radiant RTP:
Heat lamps rapidly heat the silicon wafer. Cooling is by contact with a cooled wafer holding plate. Radiant energy output from the lamps is largely in the Infra-Red (IR) range so that heating results from coupling mechanisms for IR energy to silicon. The primary coupling mechanism for heating silicon wafers is to free electrons that occur at temperatures above 700xc2x0 C. issues with Radiant RTP for future generations of semiconductor devices are
Limited temperature rise and cooling. Currently most rapid temperature rise rates that are reported are of the order of 300xc2x0 C./sec and cooling rates of the order of 90xc2x0 C./sec.
Coupling of radiant energy into the wafer is dependent on the emissivity (related to the reflectivity) of the surface and is thus dependent on the pattern and material. For fast temperature rise and cooling local pattern dependent differences do not average out and non-uniform thermal processing results.
Heating mechanism occurs only for a wafer temperature greater than 700xc2x0 C. Low temperature anneals, such as fast spike-like heating and cooling from 100xc2x0 C. to 800xc2x0 C., cannot be done.
Plasma immersion and anneal:
Instead of the scan implantation method used by ion implanters, the wafer is placed in a plasma that contains the doping material. A voltage pulse is applied to the wafer with respect to the plasma potential that drives doping ions into the wafer. A rapid thermal anneal removes the crystal damage from the plasma implant. The advantage of this approach is that it could provide ion implantation at a lower cost. Issues with this approach are the same as those set forth above for the ion implant technique as well as those above for the RTP anneal. In addition, problems include:
Obtaining full wafer doping uniformity
Controlling unwanted impurities driven into the wafer from the plasma
Projection Gas Immersion on Laser Doping (PGILD):
A laser scans the wafer in a process chamber with the doping gas. The intense, localized laser heating rapidly diffuses the doping material into the silicon. An advantage of this approach is that very high heating power can be xe2x80x9cdumpedxe2x80x9d into the surface to provide extremely rapid heating and cooling. A fundamental issue with this approach is that coupling of the laser energy into the silicon is pattern and material dependent making repeatable uniform processing difficult. Laser annealing of implanted silicon is under investigation to take advantage of the very rapid temperature rise and cool times possible. However, the fundamental issue of the silicon heating being pattern and material dependent remains.
Rapid thermal gas doping:
The wafer is placed in a furnace containing the doping material as a gas. A rapid temperature rise diffuses the doping material into the silicon. The fundamental issue with this approach for future device generations requiring shallow implants and diffusion is that temperature rise time and cool down is limited. Maximum rise times of 100xc2x0 C. using forced air oven convection have been reported.
It is known that a hot gas stream can be used to heat a substrate and that given a sufficiently intensely hot gas stream that heating could be very fast. It is generally understood in the prior art that use of intense hot gas streams tends to damage the substrate at which the stream is directed. The International Patent WO9745856, xe2x80x9cMethod for treating articles with a plasma jet,xe2x80x9d inventors Tokmouline and Siniaguine, filed 1997, considers local heating and cooling as part of a treatment process in describing motion configurations for treating batches of wafers with a plasma jet. It is not within the scope of this prior publication, and, this publication does not give consideration to use of very high temperatures, or avoiding substrate damage at high temperatures and use of very rapid cooling.
For anneal and activation RTP applications of layers, spike-like temperature rise and cooling may be needed for crystal properties of the layer and to avoid parasitic device degradation effects. Ferro-electric materials for DRAM memory devices are under investigation and require very fast RTP for anneal. Proposed high dielectric constant, xe2x80x9chigh-k,xe2x80x9d insulators for CMOS gate dielectric applications include oxide materials such as tantalum oxide. The tantalum oxide can be annealed at a temperature less than 800xc2x0 C. However, if the temperature rise and cool-down time are not sufficiently rapid, then a silicon oxide layer will form at the silicon I tantalum oxide interface partially negating the effect of the high-k tantalum oxide dielectric.
In a previously patent application of ours, which is not prior art as to the invention described herein, for processing by a hot gas generated by an atmospheric plasma, an etch application is described. This patent application is U.S. Provisional Patent application No. 60/156,407 entitled xe2x80x9cAtmospheric process and system for controlled, rapid removal of polymers from high depth to width aspect ratio holes,xe2x80x9d by inventors Bollinger and Tokmouline, filed Sep. 28, 1999 and assigned to the same assignee as for this invention. This patent application has been incorporated as part of a regular U.S. patent application filed Sep. 28, 2000 by virtue of International Patent Application PCT/US00/27113, entitled xe2x80x9cAtmospheric Process And System For Controlled And Rapid Removal of Polymers From High Depth To Width Ratio Holesxe2x80x9d, having a filing date of 28 Sep. 2000 and designating the United States. Heat flux to the subs strate in that application is typically in the range of 106-107 W/m2. Exposure times may typically be xcx9c50 ms but in a given application the exposure time may significantly vary. For etch applications, an objective is uniform net removal of material from the substrate. Since reaction rates can vary with temperature, exposure times may be adjusted significantly to compensate. Also, in etch applications the substrate should not be significantly heated. e.g., surface temperatures should be less than about 200xc2x0 C., since the processing may be done on devices further along in the manufacturing steps where the device materials may be damaged by a high temperature.
With one technique for thermal processing of substrate structures in accordance with the invention a substrate is exposed to a hot gas stream that is operated in a regime that yields a large thermal gradient through the substrate thickness during processing and is operated for a time period that is sufficiently short to enable a very rapid cool down of the areas treated by the hot gas stream.
This processing regime is obtained by a combination of high heat flux delivered to the substrate and low exposure time of any location on the substrate to the hot gas heat flux. For high temperature very fast RTP for silicon devices, with a peak temperature in the range of 1,100-1450xc2x0 C., heating power delivered to the substrate would be in a range of greater than about 5xc3x97107 Watts/m2 up to about 109 W/m2. The exposure time to the hot gas stream is chosen according to the peak temperature needed and the heating flux used and would be generally less than about 8 ms.
The uniqueness of our invention is not just the parameter range of heat flux and exposure time but that in the properly chosen combination, thermal processing can be done in a regime that preserves a large temperature differential through the substrate thickness. This will give very high heating and cooling, of the order of about xcx9c105xc2x0 C./sec, with no substrate damage or deformation. It is not only critical that exposure times be in the range to give a large temperature gradient through the substrate thickness but also that in a given RTP process the exposure times are stable and have very small variations.
With a technique in accordance with this invention Rapid Thermal Processing (RTP) of substrates, particularly semiconductor substrates for microelectronic devices and opto-electronic devices are achieved. As a result the following structures and application are obtainable:
Formation of very high electrical conductivity structures in single crystal semiconductor substrates such as silicon and compound semiconductors such as gallium arsenide.
Formation of very shallow electrically conductive structures with sharply defined doping concentration boundaries in single crystal semiconductor substrates.
Annealing and activation of deposited layers that require very rapid heating and cooling.
These structures and application are achievable because the following significant advantages of the invention arise while treating substrates for the manufacture of semi-conductor devices in accordance with the invention, namely:
A very rapid heating and cool-down of the surface of substrates with heating and cooling times greater than 103xc2x0 C./sec and can be greater than as 105xc2x0 C./sec. Such rapid heating and cooling will be needed to meet specifications for devices planned for generations beyond 2005.
Attaining a high temperature of the active surface of the substrate without permanent distortion or defects. Temperatures that can briefly melt the surface of the silicon substrate are obtainable resulting in significant improvements in electrical conductivity.
Heating of the substrate with uniform thermal processing can be achieved in a manner that is insensitive to the surface characteristics of the substrate such as patterning and material layers.
A heating method for low temperature applications can be employed using a very rapid RTP. This enables one to anneal and activate thin layers (e.g. xcx9c less than 1 micron) in temperature ranges less than 1000xc2x0 C./sec. There are a range of very fast RTP relatively low peak temperature needs, less than 1000xc2x0 C., for annealing and activating materials that would enable the manufacture of higher performance advanced devices with new materials.
With a process in accordance with the invention a particularly high degree of temperature control and uniformity, better than 1% with a corresponding high process throughput, is achievable, both within a wafer and from wafer-to-wafer. There is currently no commercially system that can meet these requirements or that is projected to do so. Except for the invention disclosed herein, we know of no method under investigation that will have the capability to meet these requirements.
With a process in accordance with this invention substrate heating can be done in two different regimes characterized by a nearly constant temperature through the substrate thickness during heating and cooling; and by a large temperature differential through the substrate thickness.
As described herein for one embodiment in accordance with the invention heating of a substrate is done by gas conduction wherein the gas heating power density is sufficiently high, preferably above about 5xc3x97107 W/m2 and with the dwell time of the substrate being treated within the hot gas stream being sufficiently low to create a high temperature gradient within the substrate. Sharply defined, shallow, high conductivity structures in silicon can be formed by rapidly bringing the silicon temperature to temperatures greater than 1100xc2x0 C. followed by very rapid cooling.
Higher conductivities can be obtained by our invention for a Rapid Thermal Process (RTP) using a very hot gas stream capable of providing a very rapid temperature rise of the substrate surface to a high temperature followed by very fast cooling. The more rapid the temperature rise and cooling, the higher the nonequilibrium doping concentration is obtained without the doping atoms agglomerating to form non-crystal defects. A very high conductivity could be obtained by an extremely fast spike-like temperature rise and cooling profile that instantaneously raises the surface of the substrate, for silicon about 1410xc2x0 C., to obtain a solubility concentration for liquid silicon.
Heating by gas conduction avoids the surface optical emissivity dependence issue of the laser and radiant RTP methods. Heat transfer to the substrate is then independent of patterning used in manufacturing microelectronic devices. Since a hot gas stream capable of carrying a high heat flux to the substrate must be used to obtain very fast RTP, a preferable approach to obtain the high heat flux is to use a gas stream that is smaller than standard substrate sizes, such as 200 mm to 300 mm diameter silicon wafers. Uniform thermal treatment is then obtained with a programmed movement of the substrate relative to the hot gas stream. To avoid hydrodynamic stabilization issues arising when one moves a hot gas stream, it is preferable, though not absolutely required, to move the substrate through a stationary hot gas stream.
Thermal treatment includes annealing or activation of the substrate surface and deposited layers, and doping of the substrate to give electrically conductive structures. Single crystal doped structures may be obtained using hot gas RTP by:
1. Thermally annealing previously implanted structures.
2. Diffusing the doping atoms into the substrate from a patterned layer deposited on the substrate surface.
3. Diffusing the doping atoms into the substrate from the hot gas stream. A hard mask, such a silicon nitride of oxide, which would be stripped in a later step, would provide the patterning for the diffusion of the doping atoms into the substrate.
Thermal treatment of this invention differs fundamentally from hot ovens approaches that use forced, convective gas flow to heat the substrate. For oven heating with convective gas flow, the gas temperature does not greatly exceed the peak temperature reached by the substrate during processing. Whereas, for a hot gas stream RTP approach in accordance with the invention, the temperature of the gas stream at the boundary layer over the substrate will be in the range of 2 to 30 times the peak temperature reached by the substrate during processing. It is this large temperature gradient established by the invention near the substrate surface that enables a very rapid heat transfer of this invention.
It is, therefore, an object of the invention to provide a process for a rapid thermal treatment involving fast heating and fast cooling of the gas treated areas of a substrate used to make semiconductor devices while using a very high temperature hot gas stream whereby excellent doping and annealing processes can be carried out to manufacture shallow substrate structures having sharp doping boundaries.
These and other objects and advantages of the invention can be understood from the following detailed description of an embodiment in conjunction with the drawings.